1. Field of the Invention
The present invention relates to a display panel driver unit into which a frame memory for storing display data is incorporated.
2. Description of the Related Art
In the liquid crystal panel incorporated into the mobile equipment, there are some cases where such a configuration is employed that a host device always sends out display data to a source driver at a frame rate of the liquid crystal. Such host device has a screen memory therein, and sends out the data in a screen memory to the source driver at a frame rate of the liquid crystal based on DMA.
When employing such configuration, since a great deal of data must be sent out at a frame rate, power consumption generated due to output capacity of the host device, capacity of the wiring connected to the panel, input capacity of the panel, and so forth as one reason is increased. Also, in order to continue the display, at least the screen memory and a DMA controller in the host device must be kept in their operative condition. Thus, power consumption generated by this reason must be taken into consideration.
It is impossible to ignore such power consumption particularly in the equipment that is required to turn on the panel constantly. Therefore, the liquid crystal panel that has a built-in memory on the source driver side and then employs a source driver of the type that rewrites data in the memory from the host device only when update of the screen occurs was put to practical use (for example, see JP-A-7-175445 (page 18, FIG. 1)).
In such display panel driver unit, there is a probability that the writing into the built-in memory to update the screen and the reading to display occur simultaneously. Therefore, a dual port memory having two-system word lines and bit lines is employed not to reduce an operation speed.
FIG. 16 is a block diagram showing a configurative example of a display panel driver unit in the prior art. In FIG. 16, the display panel driver unit is constructed, centering on a dual port memory block 43 that is able to read each row of the display screen collectively.
One port of the dual port memory block 43 is formed to read the data in one line of the panel at a time. A discharge circuit 44 and a latch circuit 48 are connected to the bit lines of this port, and the data being read from the memory into the latch circuit 48 are converted into analog signals by DACs 1.
The other port of the dual port memory block 43 is provided to load the data from the host. A precharge circuit 4, a bit line driving circuit 6, and a column selector 7 are connected to the bit lines of this port.
FIG. 17 is a circuit diagram showing detailed configurations of the dual port memory block 43, the discharge circuit 44, the latch circuit 48, the bit line driving circuit 6, and the precharge circuit 4 for one bit.
As shown in FIG. 17, in addition to the normal configuration that consists of switch transistors 62 and 63 and inverters 64 and 65, the memory cell has read-only switch transistors 82 and 83. A large number of the memory cells being aligned in a vertically and horizontally constitute the dual port memory block 43 in FIG. 16.
Then, precharge transistors 66 and 67 and a bit line driving buffer 69 are connected to bit lines HOST_BLx and # HOST_BLx of the host-side port. A large number of these elements being aligned constitute the precharge circuit 4 and the bit line driving circuit 6 in FIG. 16.
The bit line driving buffer 69 is provided to transfer the write data HOST_WD to the bit line, and drives HOST_BLx in same polarity as the HOST_WD and # HOST_BLx in opposite polarity to the HOST_WD respectively when an enable signal HOST_BEx goes to ‘1’. Then, both outputs are brought into their high-resistance state when the enable signal HOST_BEx goes to ‘0’.
The precharge transistors 66 and 67 are provided to fix electric potentials of two bit lines when the output of the bit line driving buffer 69 is in its high-resistance state, and are turned ON to set two bit lines to ‘1’ when a precharge signal #HOST_PC goes to ‘0’.
In order to access this memory cell, at first a precharge condition is released by setting #HOST_PC to ‘1’. Then, the switch transistors 62 and 63 are turned ON by setting a host-side word line HOST_WLy to ‘1’. Thus, respective states of the inverters 64 and 65 constituting the latch appear on two word lines. Read data are given by outputting the states to the column selector 7.
Also, when HOST_BLx and #HOST_BLx are driven from HOST_WD via the bit line driving buffer 69 by setting HOST_BEx to ‘1’ in the above condition, the inverters 64 and 65 are forced into the state of the bit line and thus the data writing is executed.
Meanwhile, a discharge transistor 81 and a latch 84 are connected to a bit line LCD_BLx of the display-side port. A large number of these elements being aligned constitute the discharge circuit 44 and the latch circuit 48 in FIG. 16.
This bit line is fixed to ‘0’ because the discharge transistor 81 is kept in its ON state when the reading is not being executed. In reading, first a discharge signal LCD_DC is set to ‘0’, and then a word line #LCD_WLy is set to ‘0’ to bring the switch transistor 83 into its ON state.
When ‘0’ is written into the memory cell at this time, the output of the inverter 64 becomes ‘1’ and thus the transistor 82 is in its OFF state. Therefore, the bit line LCD_BLx is kept in its ‘0’ state in a certain time. The latch 84 captures this state and thus ‘0’ is read out.
Also, when ‘1’ is written into the memory cell, the output of the inverter 64 becomes ‘0’ and thus the transistor 82 is in its ON state. Therefore, ‘1’ appears on the bit line LCD_BLx. The latch 84 captures this state and thus ‘1’ is read out.
Next, an operation of the display panel driver unit in FIG. 16 will be explained based on the circuit operations explained as above. First, signals required for a display reading operation are generated by a display-system control pulse generator circuit 45 and a line counter 9 and a row decoder 42 both being controlled by an output of the display-system control pulse generator circuit 45.
FIG. 18 is a time chart showing waveforms of the display reading operation. In FIG. 18, all circuits are operated on the basis of a horizontal synchronization clock LCLK. That is, various reference signals are output from the display-system control pulse generator circuit 45 by using a trailing edge of LCLK as a starting point.
Also, the output of the line counter 9 is changed based on a leading edge of LCLK. A word line #LCD_WLv corresponding to this output value v is driven, and the data stored in the memory cell appears on the bit line LCD_BLx. The latch 84 stores this data.
Then, signals required to execute the writing from the host are generated from a host-access control pulse generator circuit 47 operated based on signals #CS, #WE, #OE, and an address A fed from the host, and an address counter 11, a row decoder 41, and a column decoder 17.
Here, the address A fed from the host denotes a register address, and a memory address is generated from the address counter 11. An initial value of the address counter 11 is set previously by the host before starting of the writing. Then, the row decoder 41 selects the concerned word line based on HOST_ROW that is a part of the output of the address counter 11, and also the column decoder 17 selects the concerned bit line based on HOST_COL.
FIG. 19 is a time chart showing waveforms of a writing operation from the host. The waveforms needed when three pixels are written in the lateral direction are shown herein, where m is an initial value of HOST_ROW and n is an initial value of HOST_COL.
A starting point of respective signals is a #WE signal, and a data latch 19 holds input data based on the #WE. Then, #HOST_PC becomes ‘1’, and the precharge of the bit line HOST_BL is released. Then, when HOST_COL is n, a bit-line driving control signal HOST_BEn generated by the column decoder 17 goes to ‘1’. Therefore, the bit line driving circuit 6 drives a bit line HOST_BLn by the write data, and thus the data writing into the [m, n] address as the target is executed.
At this time, since bit-line driving control signals such as HOST_BEn+1, etc. are still kept in ‘0’, the data stored in the memory cell appear merely on the bit lines such as HOST_BLn+1, etc.
Subsequently, the bit line HOST_BLn+1 is driven by the write data when HOST_COL is n+1, and thus the data writing into the [m, n+1] address is executed. Then, the bit line HOST_BLn+2 is driven by the write data when HOST_COL is n+2, and thus the data writing into the [m, n+2] address is executed.
With the above configuration, in the display panel driver unit having the built-in memory, the writing from the host and the display reading can be executed independently not to lower an operation speed.
The dual port memory having the conventional structure has such a fault that a circuit area is increased since eight transistors are needed every bit and also two-system bit lines and word lines are required.
In the normal LSI, it is feasible to suppress an increase of area by applying the fine process. However, in the display panel driver unit, there is the problem that it is difficult to apply the fine process because a withstand voltage is needed to output the analog signal at a voltage that is required for the panel.